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A 512Gb In-Memory-Computing 3D-NAND Flash Supporting Similar-Vector-Matching Operations on Edge-AI Devices

Han-Wen Hu, Wei-Chen Wang, Chung-Kuang Chen, Yung-Chun Lee, Bo-Rong Lin, Huai-Mu Wang, Yen-Po Lin, Yu-Chao Lin, Chih-Chang Hsieh, Chia-Ming Hu, Yi-Ting Lai, Han-Sung Chen, Yuan-Hao Chang, Hsiang-Pang Li, Tei-Wei Kuo, Keh-Chung Wang, Meng-Fan Chang, Chun-Hsiung Hung, Chin-Yuan Lu

Research output: Chapters, Conference Papers, Creative and Literary WorksRGC 32 - Refereed conference paper (with host publication)peer-review

Abstract

Similar-vector-matching (SVM) applications for unstructured vectors that are generated via machine-learning methods, such as face search and audio texturing from a dataset for access control systems, are frequently operated on edge devices, as depicted in Fig. 7.5.1. The SVM operation [1]-[3] typically comprises of (1) in the offline phase, the extracted raw vectors (VRAW) are obtained from machine learning approaches and stored in non-volatile NAND Flash; (2) in the online phase, a processor request VRAW data from edge storage; (3) the entire VRAW dataset is moved from storage to the processor; (4) the processor scores the similarities between an input query and each candidate VRAW and provide a best match. However, the large-amount data movement across the memory hierarchy consumes a large amount of energy (EMEM), while also resulting in a long search-latency (tSR) for SVM operations. The entire VRAW dataset includes a large amount of invalid data. To reducing data movement will lower EMEM and tSR; edge storage with nonvolatile computing-in-memory (nvCIM) support for similarity computation (vector-vector multiplication (VVM) for cosine similarity) is required to reduce the VRAW dataset to a small candidate size. However, there are challenges in leveraging 3D NAND for VVM operations: (1) a low-readout accuracy when there is a large amount of current summation by using the wide range Vt-level of cells (e.g., 1st to 4th Vt-level of TLC cell) and (2) the large readout power consumption required to achieve a constant settling time against a wide range of summation currents for the possible data-patterns.
Original languageEnglish
Title of host publication2022 IEEE International Solid-State Circuits Conference, ISSCC 2022
Subtitle of host publicationDIGEST OF TECHNICAL PAPERS
PublisherIEEE
Pages138-140
ISBN (Electronic)9781665428002
ISBN (Print)9781665428019
DOIs
Publication statusPublished - Feb 2022
Externally publishedYes
Event2022 IEEE International Solid-State Circuits Conference (ISSCC 2022) - San Francisco, United States
Duration: 20 Feb 202226 Feb 2022

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume2022-February
ISSN (Print)0193-6530
ISSN (Electronic)2376-8606

Conference

Conference2022 IEEE International Solid-State Circuits Conference (ISSCC 2022)
PlaceUnited States
CitySan Francisco
Period20/02/2226/02/22

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