TY - GEN
T1 - A 1 V, compact, current-mode neural spike detector with detection probability estimator in 65 nm CMOS
AU - Yao, Enyi
AU - Basu, Arindam
N1 - Publication details (e.g. title, author(s), publication statuses and dates) are captured on an “AS IS” and “AS AVAILABLE” basis at the time of record harvesting from the data source. Suggestions for further amendments or supplementary information can be sent to [email protected].
PY - 2015/7/27
Y1 - 2015/7/27
N2 - In this paper, we describe a novel low power, compact, current-mode spike detector circuit for real-time neural recording systems where neural spikes or action potentials (AP) are of interest. Such a circuit can enable massive compression of data facilitating wireless transmission. This design operates by approximating the popularly used nonlinear energy operator (NEO) through standard current mode analog blocks that can operate at low voltages. To reduce sensitivity of threshold setting, this work uses a current-mode oscillator based detection probability estimator (DPE) to reject false positives caused by the background noise. The circuit is implemented in a 65 nm CMOS process and occupies 200 μm × 150 μm of chip area. Operating from a 1 V power supply, it consumes about 88 nW of static power and 10 nJ of dynamic energy per input spike.
AB - In this paper, we describe a novel low power, compact, current-mode spike detector circuit for real-time neural recording systems where neural spikes or action potentials (AP) are of interest. Such a circuit can enable massive compression of data facilitating wireless transmission. This design operates by approximating the popularly used nonlinear energy operator (NEO) through standard current mode analog blocks that can operate at low voltages. To reduce sensitivity of threshold setting, this work uses a current-mode oscillator based detection probability estimator (DPE) to reject false positives caused by the background noise. The circuit is implemented in a 65 nm CMOS process and occupies 200 μm × 150 μm of chip area. Operating from a 1 V power supply, it consumes about 88 nW of static power and 10 nJ of dynamic energy per input spike.
UR - https://www.scopus.com/pages/publications/84946235865
UR - https://www.scopus.com/record/pubmetrics.uri?eid=2-s2.0-84946235865&origin=recordpage
U2 - 10.1109/ISCAS.2015.7168743
DO - 10.1109/ISCAS.2015.7168743
M3 - RGC 32 - Refereed conference paper (with host publication)
SN - 9781479983919
VL - 2015-July
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 754
EP - 757
BT - 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015
PB - IEEE
T2 - IEEE International Symposium on Circuits and Systems, ISCAS 2015
Y2 - 24 May 2015 through 27 May 2015
ER -