A 0.9-5.8-GHz Software-Defined Receiver RF Front-End with Transformer-Based Current-Gain Boosting and Harmonic Rejection Calibration

Liang Wu; Alan W. L. Ng; Shiyuan Zheng; Hiu Fai Leung; Yue Chao; Alvin Li; Howard C. Luong

doi:10.1109/TVLSI.2017.2695719

Author(s)

Liang Wu
Alan W. L. Ng
Shiyuan Zheng
Hiu Fai Leung
Yue Chao
And 2 others

Alvin Li
Howard C. Luong

Related Research Unit(s)

Detail(s)

Original language	English
Article number	7918625
Pages (from-to)	2371-2382
Journal / Publication	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	25
Issue number	8
Online published	3 May 2017
Publication status	Published - Aug 2017

Link(s)

DOI	DOI https://doi.org/10.1109/TVLSI.2017.2695719 Final Published version
	Check@CityULib
Link to Scopus	https://www.scopus.com/record/display.uri?eid=2-s2.0-85019041612&origin=recordpage
Permanent Link	https://scholars.cityu.edu.hk/en/publications/publication(e2614405-2ea3-4b2e-bc86-cda10fb6f9bb).html

Abstract

A 0.9-5.8-GHz receiver RF front-end (RFE) integrating a dual-band low-noise transconductance amplifier (LNTA), a passive harmonic-rejection (HR) down-conversion mixer, and an all-digital frequency synthesizer for software-defined radios are presented. A switchable three-coil transformer acting as the interface between the LNTA and the mixer features current-gain boosting in addition to wideband operation. Automatic local oscillator phase-error detection and calibration circuitry is implemented for the mixers to achieve high HR ratio (HRR). Fabricated in 65-nm CMOS, the RFE measures the noise figure between 2.9 and 3.8 dB, the third-order input intercept point (IIP3) between -1.6 and -12.8 dBm, the third-order HRR of 81 dB, and the fifth-order HRR of 70 dB, while consuming 66-82 mA from a 1.2-V supply and occupying a chip area of 4.2 mm².

Research Area(s)

All-digital phase-locked loop (ADPLL), frequency synthesizer (FS), gain boosting, harmonic rejection (HR), low-noise transconductance amplifier (LNTA), multiband, passive mixer, RF front-end (RFE), software-defined radio (SDR), transformer

Citation Format(s)

[ RIS ] [ BibTeX ]

A 0.9-5.8-GHz Software-Defined Receiver RF Front-End with Transformer-Based Current-Gain Boosting and Harmonic Rejection Calibration. / Wu, Liang; Ng, Alan W. L.; Zheng, Shiyuan et al.
In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 25, No. 8, 7918625, 08.2017, p. 2371-2382.

Research output: Journal Publications and Reviews › RGC 21 - Publication in refereed journal › peer-review

Wu, L, Ng, AWL, Zheng, S, Leung, HF, Chao, Y, Li, A & Luong, HC 2017, 'A 0.9-5.8-GHz Software-Defined Receiver RF Front-End with Transformer-Based Current-Gain Boosting and Harmonic Rejection Calibration', IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 8, 7918625, pp. 2371-2382. https://doi.org/10.1109/TVLSI.2017.2695719

Wu, L., Ng, A. W. L., Zheng, S., Leung, H. F., Chao, Y., Li, A., & Luong, H. C. (2017). A 0.9-5.8-GHz Software-Defined Receiver RF Front-End with Transformer-Based Current-Gain Boosting and Harmonic Rejection Calibration. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 25(8), 2371-2382. Article 7918625. https://doi.org/10.1109/TVLSI.2017.2695719

Wu L, Ng AWL, Zheng S, Leung HF, Chao Y, Li A et al. A 0.9-5.8-GHz Software-Defined Receiver RF Front-End with Transformer-Based Current-Gain Boosting and Harmonic Rejection Calibration. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2017 Aug;25(8):2371-2382. 7918625. Epub 2017 May 3. doi: 10.1109/TVLSI.2017.2695719

Wu, Liang ; Ng, Alan W. L. ; Zheng, Shiyuan et al. / A 0.9-5.8-GHz Software-Defined Receiver RF Front-End with Transformer-Based Current-Gain Boosting and Harmonic Rejection Calibration. In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2017 ; Vol. 25, No. 8. pp. 2371-2382.