Abstract
A 0.9-5.8-GHz receiver RF front-end (RFE) integrating a dual-band low-noise transconductance amplifier (LNTA), a passive harmonic-rejection (HR) down-conversion mixer, and an all-digital frequency synthesizer for software-defined radios are presented. A switchable three-coil transformer acting as the interface between the LNTA and the mixer features current-gain boosting in addition to wideband operation. Automatic local oscillator phase-error detection and calibration circuitry is implemented for the mixers to achieve high HR ratio (HRR). Fabricated in 65-nm CMOS, the RFE measures the noise figure between 2.9 and 3.8 dB, the third-order input intercept point (IIP3) between -1.6 and -12.8 dBm, the third-order HRR of 81 dB, and the fifth-order HRR of 70 dB, while consuming 66-82 mA from a 1.2-V supply and occupying a chip area of 4.2 mm2.
| Original language | English |
|---|---|
| Article number | 7918625 |
| Pages (from-to) | 2371-2382 |
| Journal | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
| Volume | 25 |
| Issue number | 8 |
| Online published | 3 May 2017 |
| DOIs | |
| Publication status | Published - Aug 2017 |
Research Keywords
- All-digital phase-locked loop (ADPLL)
- frequency synthesizer (FS)
- gain boosting
- harmonic rejection (HR)
- low-noise transconductance amplifier (LNTA)
- multiband
- passive mixer
- RF front-end (RFE)
- software-defined radio (SDR)
- transformer
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