A 0.64-to-0.69THz Beam-Steerable Coherent Source with 9.1dBm Radiated Power and 30.8dBm Lensless EIRP in 65nm CMOS

Research output: Chapters, Conference Papers, Creative and Literary WorksRGC 32 - Refereed conference paper (with host publication)peer-review

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Abstract

Si-based compact terahertz (THz) integrated systems have been successfully demonstrated in imaging, spectroscopy, high-speed data transmission, and radar applications in the low-THz band [1]. A THz signal source is indispensable for applications in the mid-THz band. However, this band is beyond the fmax of most silicon-based technologies, making high-power signal generation extremely challenging. Coupled oscillator-radiator array architecture is prevalent for coherent THz signal generation and radiation [2-5]. The radiation beam narrows as the array size increases, implying a double boost in ElRP. However, most reported arrays are limited in size. Thus, the output power is small, and high ElRPs are realized by the expensive and bulky external silicon lenses [3-5]. A large array reported in [4] is 6times 7 in size but only radiates -10.9dBm at 1.01THz. Increasing the array size is not trivial. An on-chip patch-antenna-based source [2] is preferred as it can remove the silicon lens and better dissipate heat to avoid the thermal compression compared to the designs radiating from the silicon substrate [3-5]. The multi-layer topology in [2] can produce a beamforming function but lowers the DC-to-THz conversion efficiency at 416GHz. This paper proposes a differentially fed, patch-antenna-based 2D scalable array with a beamforming function and high OC-to-THz conversion efficiency. We implemented a 12times 12 coupled-oscillator array that occupies a 2textmmtimes 1.7textmn area. It can operate between 643 and 689GHz (6.9%) and radiate a peak power of 9.1 dBm with 3.32W power consumption, i.e., a 0.245 % DC-to-THz efficiency at 675GHz. The corresponding lensless ElRP is 30.8dBm, and the measured phase noise at a 1MHz offset is -90.9dBc/Hz. The beam can be steered from -45 o to 45 o in the H-plane. © 2023 IEEE.
Original languageEnglish
Title of host publication2023 IEEE International Solid-State Circuits Conference
Subtitle of host publicationDigest of Technical Papers
PublisherIEEE
Pages362-364
ISBN (Electronic)978-1-6654-9016-0
ISBN (Print)978-1-6654-2800-2
DOIs
Publication statusPublished - 2023
Event2023 IEEE International Solid-State Circuits Conference, ISSCC 2023 - Virtual, Online, United States
Duration: 19 Feb 202323 Feb 2023

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume2023-February
ISSN (Print)0193-6530

Conference

Conference2023 IEEE International Solid-State Circuits Conference, ISSCC 2023
PlaceUnited States
CityVirtual, Online
Period19/02/2323/02/23

Funding

This work is supported by the Hong Kong Research Grants Council under Grant T42- 103/16-N. The authors thank Mr. Hao Guo, Dr. Ka Fai Chan, and Dr. Kam Man Shum for their help with the chip measurement.

RGC Funding Information

  • RGC-funded

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