TY - JOUR
T1 - 60-GHz CMOS Current-Combining PA with Adaptive Back-Off PAE Enhancement
AU - Zhang, Haiwei
AU - Xue, Quan
PY - 2016/9/1
Y1 - 2016/9/1
N2 - This brief describes the design and implementation of a current-combining power amplifier (PA) with a fully adaptive approach to enhance the output power and the back-off power-added efficiency (PAE). The PA consists of a main amplifier and an auxiliary amplifier. Adaptive biasing technique is employed to shut down or provide optimum bias voltage to the auxiliary amplifier according to the input power level. The 50-$\Omega$ input matching is realized with adaptive power distribution. The output load modulation is accomplished by a compact output matching network (MN) using transmission lines and transformers. Based on the same MN, the back-off PAE degradation caused by the low output impedance of the auxiliary path is mitigated. The proposed PA is designed at 60 GHz using 65-nm CMOS and is experimentally characterized. The measurement results reveal 16-dBm OP1dB and 14% peak PAE. Approximately 8% PAE at 6-dB back-off is achieved, addressing improved back-off efficiency.
AB - This brief describes the design and implementation of a current-combining power amplifier (PA) with a fully adaptive approach to enhance the output power and the back-off power-added efficiency (PAE). The PA consists of a main amplifier and an auxiliary amplifier. Adaptive biasing technique is employed to shut down or provide optimum bias voltage to the auxiliary amplifier according to the input power level. The 50-$\Omega$ input matching is realized with adaptive power distribution. The output load modulation is accomplished by a compact output matching network (MN) using transmission lines and transformers. Based on the same MN, the back-off PAE degradation caused by the low output impedance of the auxiliary path is mitigated. The proposed PA is designed at 60 GHz using 65-nm CMOS and is experimentally characterized. The measurement results reveal 16-dBm OP1dB and 14% peak PAE. Approximately 8% PAE at 6-dB back-off is achieved, addressing improved back-off efficiency.
KW - 60 GHz
KW - Adaptive
KW - back-off efficiency
KW - CMOS
KW - current-combining
KW - power amplifier (PA)
UR - http://www.scopus.com/inward/record.url?scp=84986222467&partnerID=8YFLogxK
UR - https://www.scopus.com/record/pubmetrics.uri?eid=2-s2.0-84986222467&origin=recordpage
U2 - 10.1109/TCSII.2016.2534819
DO - 10.1109/TCSII.2016.2534819
M3 - RGC 21 - Publication in refereed journal
SN - 1549-7747
VL - 63
SP - 823
EP - 827
JO - IEEE Transactions on Circuits and Systems II: Express Briefs
JF - IEEE Transactions on Circuits and Systems II: Express Briefs
IS - 9
M1 - 7419869
ER -