Abstract
This work proposes a 3D Stack In-Sensor-Computing (3DS-ISC) architecture for efficient event-based vision processing. A real-time normalization method using an exponential decay function is introduced to construct the time-surface,reducing hardware usage while preserving temporal information. The circuit design utilizes the leakage characterization of Dynamic Random Access Memory(DRAM) for timestamp normalization. Custom interdigitated metal-oxide-metal capacitor (MOMCAP) is used to store the charge and low leakage switch (LL switch) is used to extend the effective charge storage time. The 3DS-ISC architecture integrates sensing, memory, and computation to overcome the memory wall problem, reducing power, latency, and reducing area by 69×, 2.2× and 1.9×,respectively, compared with its 2D counterpart. Moreover, compared to works using a 16-bit SRAM to store timestamps, theISC analog array can reduce power consumption by three orders of magnitude. In real computer vision (CV) tasks, we applied the spatial-temporal correlation filter (STCF) for denoise, and3D-ISC achieved almost equivalent accuracy compared to the digital implementation using high precision timestamps. As for the image classification, time-surface constructed by 3D-ISC is used as the input of GoogleNet, achieving 99% on N-MNIST,85% on N-Caltech101, 78% on CIFAR10-DVS, and 97% on DVS128 Gesture, comparable with state-of-the-art results on each dataset. Additionally, the 3D-ISC method is also applied to image reconstruction using the DAVIS240C dataset, achieving the highest average SSIM (0.62) among three methods. This work establishes a foundation for real-time, resource-efficient event based processing and points to future integration of advanced computational circuits for broader applications.
© 2025 IEEE. All rights reserved, including rights for text and data mining, and training of artificial intelligence and similar technologies. Personal use is permitted, but republication/redistribution requires IEEE permission.
© 2025 IEEE. All rights reserved, including rights for text and data mining, and training of artificial intelligence and similar technologies. Personal use is permitted, but republication/redistribution requires IEEE permission.
| Original language | English |
|---|---|
| Number of pages | 14 |
| Journal | IEEE Transactions on Circuits and Systems I: Regular Papers |
| Online published | 5 Jan 2026 |
| DOIs | |
| Publication status | Online published - 5 Jan 2026 |
Funding
This work was supported in part by the Research Grants Council (RGC) under Grant C7003-24Y and in part by the Innovation Technology Fund Mid-Stream Research Program under Grant ITS/018/22MS.
Research Keywords
- Random access memory
- Computer architecture
- Three-dimensional displays
- Hardware
- Circuits
- Stacking
- Memristors
- Image reconstruction
- Event detection
- Voltage control
- Dynamic vision sensor
- neuromorphic
- 3D integration
- eDRAM
- event based sensor
RGC Funding Information
- RGC-funded
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Dive into the research topics of '3D Stack In-Sensor-Computing (3DS-ISC): Accelerating Time-Surface Construction for Neuromorphic Event Cameras'. Together they form a unique fingerprint.Projects
- 2 Active
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YCRG-ExtU-Lead: Heterogenous In-memory Computing hardware Technologies for Fast and Efficient Genomic Analysis
Li, C. (Main Project Coordinator [External]), BASU, A. (Principal Investigator / Project Coordinator), HUANG, Y. (Co-Principal Investigator), LUO, R. (Co-Principal Investigator), STRACHAN, J. P. (Co-Principal Investigator) & WANG, H. (Co-Principal Investigator)
1/05/25 → …
Project: Research
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ITF: Reconfigurable Nonlinear In-memory Computations: A Pathway to Low-power, Recurrent Neural Networks
BASU, A. (Principal Investigator / Project Coordinator) & LI, H. (Co-Investigator)
1/09/23 → …
Project: Research
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