20-40 GHz dual-gate frequency doubler using 0.5 μm GaAs pHEMT technology

Research output: Journal Publications and Reviews (RGC: 21, 22, 62)21_Publication in refereed journal

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Author(s)

  • Yuan Chun Li
  • Fan-Hsiu Huang
  • Quan Xue

Related Research Unit(s)

Detail(s)

Original languageEnglish
Pages (from-to)758-759
Journal / PublicationElectronics Letters
Volume50
Issue number10
Publication statusPublished - 8 May 2014

Abstract

A Ka-band dual-gate frequency doubler using 0.5 μm GaAs enhancement- mode pHEMT process is presented. The cascode circuit is equalised to the dual-gate frequency doubler and the relationship between bias and output matching is discussed to obtain the maximum output power and conversion efficiency. Since a pinch-off gate-to-source bias is driven at the input gate node, the frequency doubler consumes little DC power when injecting a low-power fundamental signal. Based on the analysis, the designed dual-gate doubler has a 3 dB bandwidth of 5.6 GHz, from 36 to 41.6 GHz. The fundamental suppressions are better than 15 dB. The measured maximum conversion gain is -0.9 dB at an injected power of 7 dBm. A high saturation output power is 7 dBm with a conversion efficiency of 14.3%. The measured results confirm the validity of the proposed analysis method. © The Institution of Engineering and Technology 2014.

Citation Format(s)

20-40 GHz dual-gate frequency doubler using 0.5 μm GaAs pHEMT technology. / Li, Yuan Chun; Huang, Fan-Hsiu; Xue, Quan.

In: Electronics Letters, Vol. 50, No. 10, 08.05.2014, p. 758-759.

Research output: Journal Publications and Reviews (RGC: 21, 22, 62)21_Publication in refereed journal