Abstract
This paper describes a novel design method of real time video processing, de-interlacing, color transient improvement and color space conversion, which is suitable for VLSI implementation. A synchronous and parallel pipeline architecture is proposed to reduce the complexity of video processing. The hardware design based on IP (intellectual property) module of SOC (system on a chip) is also discussed. This design is verified by Synopsys EDA tool based on 0.35 μm CMOS.
| Translated title of the contribution | VLSI Implementation for Video Processing IP Module Based on Synchronous and Parallel Architecture |
|---|---|
| Original language | Chinese (Simplified) |
| Pages (from-to) | 945-948 |
| Journal | 电子学报 |
| Volume | 30 |
| Issue number | 7 |
| Publication status | Published - Jul 2002 |
| Externally published | Yes |
Research Keywords
- 同步并行结构
- 视频处理
- IP 模块
- VLSI 结构
- synchronous and parallel architecture
- video processing
- IP module
- VLSI architecture
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