Realization and Characterization of Half-Static Clock-Gating D-Type Flip-Flop

The wide application of CMOS integrated circuits in portable consumer products has led to substantial demand on high power efficient digital circuits. The larger off-current in recent nanoscale CMOS transistors also requires the circuits and systems to have better power efficiency. Sequential circuits in digital systems are often realized using D-type flip-flops (FFs). The FFs contribute the most significant portion of the total power dissipation in these circuits. Hence, a better power efficiency D-type FF will substantially save the total power dissipation in these circuits. The research team has recently developed a high-performance half-static clock-gating (HSCG) D-type flip-flop based on a dynamic master and half-static slave structure and additional pass-transistor clock-gating circuit. Preliminary results showed that the proposed flip-flop has many outstanding characteristics such as better timing flexibility, higher power efficiency, and smaller chip size when compared with the existing D-type FFs. This project aims at the realization and better characterization of this circuit.