Non-Volatile Memory Based Hybrid Caches and Memories for Low Power and High Performance Systems

Power efficiency is becoming a critical issue across all types of computing domains, from mobile devices, PCs, to supercomputers. Studies have shown that memory and cache consume over 60% of the power in most of computing systems. As semi-conductor technology advance into sub-micro levels, static power is surpassing dynamic power and becoming the dominant factor in power consumption. While the processor technology has grown exponentially in the last quarter of century along with the semi-conductor advancement, memory technology has been lagging behind. In the last couple of years, exciting developments in memory technology aim to solve the power efficiency issue as well as bring memory technology leaping forward.New memory developments center on Non-volatile Memories (NVM), such as Phase Change Memory (PCM), Spin Torque Transfer RAM (STT-RAM), Flash Memory. These memories have the characteristics of non-volatility, shock-resistivity, high density and power-economy. At the same time, there are limitations on non-volatile memories. Write operations on non-volatile memories usually incur higher latency or energy, and non-volatile memories often have limited lifetimes bounded by the number of write operations. Cost is another factor that is limiting the wide adoption of large-scale non-volatile memories. It is observed that neither pure SRAM/DRAM nor pure NVM is the best solution for low power and high performance systems. With the goal of obtaining all the benefits of NVM while retaining the write efficiency and cost efficiency of SRAM/DRAM, in this project, we propose hybrid caches and memories based on NVM for practical low power and high performance systems.Memories and caches are often organized into hierarchical structures in a computing system. This project intends to build hybrid memory solutions on four levels: hybrid scratch-pad memory, hybrid last-level cache, hybrid main memory, and hybrid disk cache. There are common ideas and techniques that can be shared and applied to all four levels, for example, data allocation between different parts of the hybrid memory based on the read and write characteristics. At each level, armed with different information available and along with different settings, we have identified different perspectives to develop unique, effective, and efficient hybrid solutions. Synergies among these four levels will lead to the success of this project as a whole.The future of memory is NVM based hybrid cache and memories. This project will make significant contributions to memory and cache research and the results can be applied directly in several vital industries of Hong Kong.