NEUCOME: Neuromorphic Compression and Memory Management for next-generation Implantable Brain-machine Interfaces
- Arindam BASU (Principal Investigator / Project Coordinator)Department of Electrical Engineering
- Rosa Qi Yue SO (Co-Investigator)
DescriptionA promising technology to restore the communication and locomotion function of patients suffering from paralysis is intra-cortical Brain-Machine Interface (iBMI). The significant challenges for such implantable iBMI systems include a wired connection to computers that reduce mobility, holes in the skull for wiring that may lead to infections, and a limited number of sensor channels that provide fewer data. This proposal aims to overcome these challenges using a novel integrated circuit techniques and architectures to compress the data to meet wireless transmission bitrates and power dissipation limits while increasing sensor channel count. No solution exists for managing the increasing data generated by tens of thousands of sensor channels. This increased data requires a large area and power dissipation due to memory size. One solution may be enabled by the sparsity of neural signals –neural spikes that carry information exist only for ~2% of the time resulting in high energy efficiencies of the brain. We propose two neuromorphic architectures to exploit this sparsity. In the first architecture, we propose to use a hashing-bashed method from computer architecture to map the output of the high-dimensional sensor array to a smaller-sized memory. A hash function can be generally thought of as any function that can map the input of an arbitrary range of values to an output of a fixed range. A prime consideration here is to minimize collisions, i.e., to avoid neural data from one active channel to overwrite that of another active channel. These collisions may vary based on the sensor type and brain region of implantation. To this end, we propose to use machine learning techniques to identify the ideal parameters of the hash function. In the second architecture, we propose to use change-detection-based amplifier pixels in the sensor array that only output sparse, asynchronous, digital pulses when the input changes by a significant amount. This method provides data compression, but the digital pulses are asynchronous and hence not compatible with standard memory. We propose a new hybrid memory that combines DRAM for analog compute in-memory with SRAM for long-term digital storage. Both methods are estimated to provide 6-8X reduction in power dissipation and will be validated by custom integrated circuit designs that will be tested with pre-recorded data from iBMI systems. We expect the output of this interdisciplinary project to influence future generations of iBMI and other neuro-technologies for translation and fundamental research.
|Effective start/end date||1/01/23 → …|