Memory Access and Task Scheduling Optimization for Embedded Systems

While the advance of semiconductor technology enables processor speed to double approximately every eighteen months, main memory speed doubles only about every ten years. These diverging rates imply an impending “Memory Wall,” i.e., memory accesses can dominate system performance. The memory-wall problem becomes even more serious when throughput in the processor parts is propelled by multi-core or multiprocessor architectures. Embedded systems often need to access memory extensively. For example, for real-time Digital Signal Processing applications and video processing embedded systems, data accessing speed is often the main bottleneck of achieving higher performance.To reduce the gap between memory and processor performance, extensive work has been done for general purpose computing systems. For embedded systems, advantage can be taken from the application-specific information to improve the memory performance further. This project aims to improve overall system performance by improving memory performance. This project is set to explore new techniques to optimize memory access and task scheduling for embedded systems. In particular, this project will focus on solving two problems: task scheduling for memory access optimization and memory customization for embedded chip multiprocessors.In task scheduling for memory access optimization, a fundamental study of the effect on memory access by task scheduling will be carried out. Most of the previous work in reducing the memory performance gap either does not consider scheduling at all, or it takes a fixed schedule as its input. Scheduling has been identified as having a profound impact on memory access operations. Theoretical frameworks will be developed to model the fundamental properties. Scheduling techniques will be designed and implemented to minimize memory access on different architectures.For embedded chip multiprocessors, customized memories are often designed for different optimization goals. Some previous works proposed techniques to design customized memories to achieve lower power consumption than conventional memory architecture. There is no previous work that considers the timing effect via task scheduling and memory customization. In this project, timing performance effect will be explored when designing a customized memory. Techniques will be developed to conduct memory customization and scheduling jointly.Reducing the memory and processor performance gap is extremely critical for developing high performance embedded systems. It is believed that this project will make significant contributions to embedded system research, and the results can be applied directly in several vital industries of Hong Kong.