Intelligent Gate Drive Architecture

Description

Basic bridge leg, which consists of two power devices connected in series and alternately switched, has been widely used in power electronics systems. It is well known that parasitic elements of those devices can cause undesirable crosstalk. Spurious triggering signals may be generated and applied to the device that should be turned off. Such phenomenon causes short circuit of the supply and high current pulses, thereby generating electromagnetic interference and shortening device life. Wide bandgap switching devices, such as SiC and GaN, have become increasingly popular. Their gate drive requirements are more stringent than traditional silicon-based devices in handling crosstalk and reducing reverse conduction power losses to ensure reliable and efficient operation. Prior art requires sophisticated structures, resulting in increased power consumption and circuit complexity. Moreover, the devices are not optimally driven as their driving profiles are predefined at the design stage. This project aims to develop an intelligent gate drive architecture for SiC-based bridge leg to address the above issues. The architecture can profile the gate signal level adaptively and optimally to deal with crosstalk and maintain low off-state gate voltage to lower reverse conduction power losses and gate voltage stress. It can also perform real-time device degradation monitoring.