ESD Protection for 22nm CMOS Technology

Project: Research

View graph of relations

Description

Electrostatic discharge (ESD) is one of the major causes for the fatal failure of electronic components. The transient electrostatic voltage generated by a human body or by a machine may exceed several thousand volts, a value which is large enough to instantly melt the metal interconnects in an integrated circuit (IC) and to produce thermal runaway of a semiconductor material. ESD often strikes on a component during its manufacturing, transportation, during the assembly process on a printed circuit board, as well as during the daily operation of an electronic product. Consequently, many efficient ESD protection devices have been developed to secure the operation and to enhance the robustness of electronic products. However, with the newly developed 22 nm fabrication technology for the next generation of CMOS ICs, a number of new challenges came up. The 22 nm transistors are known to be operated at much smaller voltages because of their thinner gate oxide and their shorter gate length, which make these devices more vulnerable to various ESD-related damages. Lower voltage operation conditions require new ESD protection devices that must be still as robust as those used in the previous technology nodes. This narrowed design window would impose the development of some new device structures. The present work aims at developing some novel ESD protection devices/schemes for the 22 nm technology applications. We shall focus on structures based on silicon-controlled rectifier (SCR), with some low-voltage triggering schemes and electric field redistribution techniques to achieve a high robustness and high-efficient ESD protection.

Detail(s)

Project number9041919
Grant typeGRF
StatusFinished
Effective start/end date1/01/1414/11/18