Energy Efficient Scheduling in DVS Processors with Accelerations for Jobs with Multiple Active Intervals

Description

Energy efficient scheduling is considered an important way to extend the lifetime of battery-powered portable electronic devices. Current dynamic voltage scaling (DVS) techniques allow the speed of processors to be set dynamically and therefore make it possible to save energy by scheduling jobs wisely. The associated scheduling problems for DVS techniques can be classified into three categories: the ideal model, the multiple model, and the feasible model. The model that characterizes the real system most accurately is the feasible model, where there is some acceleration constraint on the speed change and at the same time there is a maximum speed and a minimum speed requirement. The principal goal of this project is to design algorithms to compute the minimum energy schedule for the feasible model. A new type of jobs, with multiple release times and deadlines, will be introduced. Such a job is considered to be completed if it is assigned enough CPU cycles within all of its active intervals. The researchers will study the characteristics of the min-energy schedule for the new type of job sets in all the three categories of DVS models. The project outcomes will lead to deeper insights in DVS scheduling algorithms and therefore provide useful information for chip designers.