Energy Efficient Schedules on Clustered DVS Processors with Partitioned Memory

The advocation of green computing in recent years reflects researchers' intention to save more energy and resources for sustainability. The advance of computer hardware technology witnesses new types of processors which not only provide more computation power but also pose new challenges on designing energy efficient scheduling algorithms.In this proposal, we focus on energy efficient schedules in clustered DVS multi-core architecture with memory constraints. In a multi-core system, providing one global supply voltage for all cores will be energy-inefficient while providing individual supply voltage for each core locally can be energy-efficient but costly for implementation. A tradeoff between the global- and local-voltage platforms is to adopt a multi-core architecture with different voltage clusters, in which several cores in a voltage cluster share the same but adjustable supply voltage. For example, Intel has recently released a research multi-core platform, called Single-chip Cloud Computer, in which 48 cores are divided into 6 clusters, each with 8 cores. We will try to identify optimal schedules when the jobs are already assigned to cores and also find guidelines on how to assign jobs to achieve energy efficiency.Besides the energy consumption by the processors, another major source of energy con- sumption is the memory. Researchers have shown that the static energy consumption for keeping the memory active already takes a substantial part in the whole memory energy consumption. Hence, how to execute the jobs in such a way that the total memory idle time is as long as possible becomes an important research problem. From the theoretical computer science community, researchers studied the single processor case where processor idle time is equivalent to memory idle time, while the practical community explored many useful heuristic rules to reduce the memory energy consumption by turning memory on and oR. However, for the multi-core system where different cores share the same memory, how to group idle time from processors into memory idle time is a not yet tackled problem theoret- ically. Furthermore, different memory architectures allow different optimization flexibilities. For example, some memory is divided into banks and each bank can be turned on and oR in- dependently. Providing theoretical guarantee on energy saving for different types of memory will be both challenging and worth exploring.Completing this project will lead to deeper insights into energy efficient scheduling in a more complete computing system and hence speed up incorporating energy efficient algo- rithms into the operating systems.