Digital Watermarking Chip Design

The demand of a reliability watermarking algorithm and ultimately a security protection chip increases as digital documents in the form of digital images becoming popular. Steganography is a method of hiding secret data into an cover image such that no one can detect the existence of such hided data. In this project, we will first study the integrity of high payload steganographic schemes, design reliable error recovery protocols, evaluate their feasibility for ASIC implementation and finally design, simulate and fabricate a suitable real time digital watermarking chip that is robust enough for withstanding most digital/image processing attacks. The implementation will be based on FPGA then ASIC implementation.