Characterization and Modeling of MOS Transistors based on Stacked Silicon Nanowires

According to the prediction made by the International Technology Roadmap for Semiconductor (ITRS), the downsizing of the metal-oxide-semiconductor (MOS) transistor will go on for some more decades and eventually sub-decananometer gate length MOS transistor will be used in future semiconductor manufacturing. However, new device structures and new fabrication processes are to be developed in order to maintain this trend. Silicon nanowire (SiNW) MOS transistors are considered to be the most promising devices for the ultimate technology node in the sub-decananometer range due to their simple fabrication process and excellent immunity to short-channel effects. However, many properties of this new type of transistor are still unexplored and some of the device characteristics, as well as its fabrication process, still need tremendous improvements before this type of device can be used in actual integration circuit (IC) manufacturing. This work aims at fabricating and characterizing SiNW MOS transistors. Based on the proposed experiments, we shall develop some optimal processes for the device fabrication; we shall also develop some theoretical models to explain and to predict the performances of the transistors so as to provide useful guidelines for designing high-performance SiNW MOS device and rules for its applications in future CMOS integrated circuits.