A Study of Nanostructured Electronic Interconnects - Preparation, Characterization and Integration

Project: Research

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The rapid advances in the miniaturization of chip-scale packaging technologies have prompted a rapid increase in the density of solder joints in microelectronic devices. The integrated circuits (ICs) are beginning to move to nano-scale with less than 100nm lithography, 100 million transistors, requiring more than 10,000 input/outputs (I/Os) on a 10-40 micrometers area array pitch. Downscaling traditional solder bump interconnects will not satisfy the thermo-mechanical reliability requirements at very fine pitches (<20 micromeres). Lead-free interconnect reliability has been a concern due to interfacial intermetallic compounds and high temperature reflow problems. The reliability of electronic products relating to the mechanical properties of intermetallic compound layers is even more important now than before. This is especially true for portable products, which frequently experience mechanical shock loadings caused by dropping. There is no way to solve future problems except with an increasing knowledge-base for lead-free interconnect through an in-depth of understanding the relationship between the microstructure and mechanical behavior. As new materials emerge, and the industry incorporates many different materials into the assembly process, it is also critical to be able to describe the interactions between materials and process parameters, and accurate characterization is an important pre-requisite to achieve high yield and reliability. However, nanophase and nanostructured materials, a new branch of materials research, are attracting a great deal of attention because of their unique properties and improved performances. This project will explore the modification of interconnect microstructures to nanostructures in ultra-fine lead-free solder joints for high density chip-tosubstrate interconnections under combined electro-thermo-mechanical-chemical loading. Therefore, systematically modifying interconnect microstructures to nanostructures will be investigated with various service loadings individually as well as cumulatively in the proposed project. Under-bump-metallization (UBM) dissolution, intermetallic compound (IMC) formation, current crowding, atomic migration, plastic flow, and void formation in solder joints will be investigated using a Physics-of-Failure (PoF) approach in conjunction with revolutionized concepts of high temperature aging, various temperature/relative humidity (RH) (65 deg C/65%, 85 deg C/85%) testing, thermo mechanical fatigue (TMF) testing, vibration and mechanical shock via dynamic mechanical testing. Failure distribution during accelerated tests will be extrapolated to reveal the service life of electronic products based on the PoF mechanisms. It is expected that this novel PoF approach coupled with carefully planned Design-of-Experiments (DoE) will revolutionize the reliability in nanostructure interconnects and interfaces, thus laying a strong foundation for a better scientific understanding of the capabilities and limitations of such physical phenomena in nanoelectronics applications.


Project number9041636
Grant typeGRF
Effective start/end date1/12/1126/10/15