Dr. HUANG Weipei (黃維沛)

Research Output

  1. 2021
  2. Published

    An Efficient Parallel Processor for Dense Tensor Computation

    Huang, W.-P., Cheung, R. C. C. & Yan, H., Jul 2021, In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 29, 7, p. 1335-1347

    Research output: Journal Publications and ReviewsRGC 21 - Publication in refereed journalpeer-review

    Scopus citations: 2
    Check@CityULib
  3. 2019
  4. Published

    An efficient application specific instruction set processor (ASIP) for tensor computation

    Huang, W.-P., Cheung, R. C. C. & Yan, H., Jul 2019, Proceedings - 2019 IEEE 30th International Conference on Application-Specific Systems, Architectures and Processors (ASAP 2019). Institute of Electrical and Electronics Engineers, Inc., p. 37 8825140. (Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors; vol. 2019-July).

    Research output: Chapters, Conference Papers, Creative and Literary WorksRGC 32 - Refereed conference paper (with host publication)peer-review

    Scopus citations: 3
    Check@CityULib
  5. Published

    A high performance hardware architecture for non-negative tensor factorization

    Min, B., Huang, W.-P., Cheung, R. C. C. & Yan, H., Mar 2019, In: Microelectronics Journal. 85, p. 25-33

    Research output: Journal Publications and ReviewsRGC 21 - Publication in refereed journalpeer-review

    Scopus citations: 2
    Check@CityULib
  6. Published

    High performance hardware architecture for singular spectrum analysis of Hankel tensors

    Huang, W.-P., Kwan, B. P. Y., Ding, W., Min, B., Cheung, R. C. C., Qi, L. & Yan, H., Feb 2019, In: Microprocessors and Microsystems. 64, p. 120-127

    Research output: Journal Publications and ReviewsRGC 21 - Publication in refereed journalpeer-review

    Scopus citations: 2
    Check@CityULib