Mr. HUANG Weipei (黃維沛)

Research Output

  1. 2019
  2. Published

    An efficient application specific instruction set processor (ASIP) for tensor computation

    Huang, W., Cheung, R. C. C. & Yan, H., Jul 2019, Proceedings - 2019 IEEE 30th International Conference on Application-Specific Systems, Architectures and Processors (ASAP 2019). IEEE, p. 37 8825140. (Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors; vol. 2019-July).

    Research output: Chapters, Conference Papers, Creative and Literary Works (RGC: 12, 32, 41, 45)32_Refereed conference paper (with ISBN/ISSN)peer-review

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  3. Published

    A high performance hardware architecture for non-negative tensor factorization

    Min, B., Huang, W., Cheung, R. C. C. & Yan, H., Mar 2019, In : Microelectronics Journal. 85, p. 25-33

    Research output: Journal Publications and Reviews (RGC: 21, 22, 62)21_Publication in refereed journalpeer-review

    Scopus citations: 1
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  4. Published

    High performance hardware architecture for singular spectrum analysis of Hankel tensors

    Huang, W., Kwan, B. P. Y., Ding, W., Min, B., Cheung, R. C. C., Qi, L. & Yan, H., Feb 2019, In : Microprocessors and Microsystems. 64, p. 120-127

    Research output: Journal Publications and Reviews (RGC: 21, 22, 62)21_Publication in refereed journalpeer-review

    Scopus citations: 1
    Check@CityULib