IEEE Transactions on Very Large Scale Integration (VLSI) Systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

ISSNs: 1063-8210

Additional searchable ISSN (Electronic): 1557-9999

Institute of Electrical and Electronics Engineers, United States

Scopus (2020), Scopus (2020), Scopus (2020), Scopus rating (2021)

Journal

Journal Metrics
1 - 20 out of 20Page size: 20

Research Output

  1. 2020
  2. Published

    RPE-TCAM: Reconfigurable Power-Efficient Ternary Content-Addressable Memory on FPGAs

    Irfan, M., Ullah, Z., Chowdhury, M. H. & Cheung, R. C. C., Aug 2020, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 28, 8, p. 1925-1929 9099062.

    Research output: Journal Publications and Reviews (RGC: 21, 22, 62) › 21_Publication in refereed journal › peer-review

    Scopus citations: 2
    Check@CityULib
  3. 2018
  4. Published

    PATH: Performance-Aware Task Scheduling for Energy-Harvesting Nonvolatile Processors

    Li, J., Liu, Y., Li, H., Yuan, Z., Fu, C., Yue, J., Feng, X. & 3 others, Xue, C. J., Hu, J. & Yang, H., Sep 2018, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 26, 9, p. 1671-1684

    Research output: Journal Publications and Reviews (RGC: 21, 22, 62) › 21_Publication in refereed journal › peer-review

    Scopus citations: 5
    Check@CityULib
  5. Published

    Memory-Based Architecture for Multicharacter Aho-Corasick String Matching

    Wang, X. & Pao, D., Jan 2018, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 26, 1, p. 143-154

    Research output: Journal Publications and Reviews (RGC: 21, 22, 62) › 21_Publication in refereed journal › peer-review

    Scopus citations: 7
    Check@CityULib
  6. 2017
  7. Published

    DVFS-Based Long-Term Task Scheduling for Dual-Channel Solar-Powered Sensor Nodes

    Wu, T., Liu, Y., Zhang, D., Li, J., Hu, X. S., Xue, C. J. & Yang, H., Nov 2017, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 25, 11, p. 2981-2994 8016408.

    Research output: Journal Publications and Reviews (RGC: 21, 22, 62) › 21_Publication in refereed journal › peer-review

    Scopus citations: 1
    Check@CityULib
  8. Published

    A 0.9-5.8-GHz Software-Defined Receiver RF Front-End with Transformer-Based Current-Gain Boosting and Harmonic Rejection Calibration

    Wu, L., Ng, A. W. L., Zheng, S., Leung, H. F., Chao, Y., Li, A. & Luong, H. C., Aug 2017, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 25, 8, p. 2371-2382 7918625.

    Research output: Journal Publications and Reviews (RGC: 21, 22, 62) › 21_Publication in refereed journal › peer-review

    Scopus citations: 6
    Check@CityULib
  9. Published

    CP-FPGA: Energy-Efficient Nonvolatile FPGA with Offline/Online Checkpointing Optimization

    Yuan, Z., Liu, Y., Li, J., Hu, J., Xue, C. J. & Yang, H., Jul 2017, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 25, 7, p. 2153-2163 7889029.

    Research output: Journal Publications and Reviews (RGC: 21, 22, 62) › 21_Publication in refereed journal › peer-review

    Scopus citations: 3
    Check@CityULib
  10. Published

    Maximizing Common Idle Time on Multicore Processors with Shared Memory

    Fu, C., Zhao, Y., Li, M. & Xue, C. J., Jul 2017, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 25, 7, p. 2095-2108 14 p., 7869408.

    Research output: Journal Publications and Reviews (RGC: 21, 22, 62) › 21_Publication in refereed journal › peer-review

    Scopus citations: 2
    Check@CityULib
  11. 2016
  12. Published

    Efficient Data Placement for Improving Data Access Performance on Domain-Wall Memory

    Chen, X., Sha, E. H., Zhuge, Q., Xue, C. J., Jiang, W. & Wang, Y., 1 Oct 2016, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 24, 10, p. 3094-3104 7445241.

    Research output: Journal Publications and Reviews (RGC: 21, 22, 62) › 21_Publication in refereed journal › peer-review

    Scopus citations: 15
    Check@CityULib
  13. Published

    Exploiting Process Variation for Write Performance Improvement on NAND Flash Memory Storage Systems

    Shi, L., Di, Y., Zhao, M., Xue, C. J., Wu, K. & Sha, E. H., 1 Jan 2016, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 24, 1, p. 334-337 7041199.

    Research output: Journal Publications and Reviews (RGC: 21, 22, 62) › 21_Publication in refereed journal › peer-review

    Scopus citations: 20
    Check@CityULib
  14. 2015
  15. Published

    Joint profit and process variation aware high level synthesis with speed binning

    Zhao, M., Orailoglu, A. & Xue, C. J., 1 Sep 2015, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 23, 9, p. 1640-1650 6893057.

    Research output: Journal Publications and Reviews (RGC: 21, 22, 62) › 21_Publication in refereed journal › peer-review

    Scopus citations: 1
    Check@CityULib
  16. Published

    Low Overhead Software Wear Leveling for Hybrid PCM + DRAM Main Memory on Embedded Systems

    Hu, J., Xie, M., Pan, C., Xue, C. J., Zhuge, Q. & Sha, E. H., Apr 2015, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 23, 4, p. 654-663 6820777.

    Research output: Journal Publications and Reviews (RGC: 21, 22, 62) › 21_Publication in refereed journal › peer-review

    Scopus citations: 24
    Check@CityULib
  17. Published

    Z-TCAM: An SRAM-based architecture for TCAM

    Ullah, Z., Jaiswal, M. K. & Cheung, R. C. C., Feb 2015, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 23, 2, p. 402-406 6774983.

    Research output: Journal Publications and Reviews (RGC: 21, 22, 62) › 21_Publication in refereed journal › peer-review

    Scopus citations: 47
    Check@CityULib
  18. 2014
  19. Published

    A unified write buffer cache management scheme for flash memory

    Shi, L., Li, J., Li, Q., Xue, C. J., Yang, C. & Zhou, X., Dec 2014, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 22, 12, p. 2779-2792 6705640.

    Research output: Journal Publications and Reviews (RGC: 21, 22, 62) › 21_Publication in refereed journal › peer-review

    Scopus citations: 9
    Check@CityULib
  20. Published

    Compiler-assisted STT-RAM-based hybrid cache for energy efficient embedded systems

    Li, Q., Li, J., Shi, L., Zhao, M., Xue, C. J. & He, Y., Aug 2014, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 22, 8, p. 1829-1840 6588311.

    Research output: Journal Publications and Reviews (RGC: 21, 22, 62) › 21_Publication in refereed journal › peer-review

    Scopus citations: 31
    Check@CityULib
  21. Published

    WCET-Aware re-scheduling register allocation for real-time embedded systems with clustered VLIW Architecture

    Huang, Y., Shi, L., Li, J., Li, Q. & Xue, C. J., Jan 2014, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 22, 1, p. 168-180 6414665.

    Research output: Journal Publications and Reviews (RGC: 21, 22, 62) › 21_Publication in refereed journal › peer-review

    Scopus citations: 6
    Check@CityULib
  22. 2013
  23. Published

    Task allocation on nonvolatile-memory-based hybrid main memory

    Tian, W., Zhao, Y., Shi, L., Li, Q., Li, J., Xue, C. J., Li, M. & 1 others, Chen, E., Jul 2013, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 21, 7, p. 1271-1284 6268363.

    Research output: Journal Publications and Reviews (RGC: 21, 22, 62) › 21_Publication in refereed journal › peer-review

    Scopus citations: 19
    Check@CityULib
  24. Published

    Data allocation optimization for hybrid scratch pad memory with SRAM and nonvolatile memory

    Hu, J., Xue, C. J., Zhuge, Q., Tseng, W. & Sha, E. H., Jun 2013, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 21, 6, p. 1094-1102 6248275.

    Research output: Journal Publications and Reviews (RGC: 21, 22, 62) › 21_Publication in refereed journal › peer-review

    Scopus citations: 46
    Check@CityULib
  25. Published

    Cooperating virtual memory and write buffer management for flash-based storage systems

    Shi, L., Li, J., Xue, C. J. & Zhou, X., 2013, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 21, 4, p. 706-719 6193235.

    Research output: Journal Publications and Reviews (RGC: 21, 22, 62) › 21_Publication in refereed journal › peer-review

    Scopus citations: 10
    Check@CityULib
  26. 2012
  27. Published

    Decentralized and passive model order reduction of linear networks with massive ports

    Yan, B., Tan, S. X., Zhou, L., Chen, J. & Shen, R., May 2012, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 20, 5, p. 865-877 5741877.

    Research output: Journal Publications and Reviews (RGC: 21, 22, 62) › 21_Publication in refereed journal › peer-review

    Scopus citations: 9
    Check@CityULib
  28. 2011
  29. Published

    Energy-efficient joint scheduling and application-specific interconnection design

    Xu, C. Q., Xue, C. J. & Sha, E. H., Oct 2011, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 19, 10, p. 1813-1822 5565543.

    Research output: Journal Publications and Reviews (RGC: 21, 22, 62) › 21_Publication in refereed journal › peer-review

    Scopus citations: 3
    Check@CityULib