PUF-Enhanced Processor Design for Image Encryption (Datasets)

Dataset

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Researcher(s)

Research Unit(s)

External organisation(s)

  • University of Southampton

Description

PUF-Enhanced Processor Design for Image Encryption (datasets).
All the hardware experimental data were collected from 8 equal FPGA development kits and a test manual is included.
Devices: Artix-7 FPGA (XC7A100TCSG324-1). IDE Version: Vivado-2020.1.
Date made available20 Nov 2022
PublisherIEEE DataPort
Date of data production20 Nov 2022
Legal/ethicalCommercial constraints: This dataset requires an IEEE DataPort Subscription.

Link(s)

DOI

DOI