Description
PUF-Enhanced Processor Design for Image Encryption (datasets).
All the hardware experimental data were collected from 8 equal FPGA development kits and a test manual is included.
Devices: Artix-7 FPGA (XC7A100TCSG324-1). IDE Version: Vivado-2020.1.
All the hardware experimental data were collected from 8 equal FPGA development kits and a test manual is included.
Devices: Artix-7 FPGA (XC7A100TCSG324-1). IDE Version: Vivado-2020.1.
| Date made available | 20 Nov 2022 |
|---|---|
| Publisher | IEEE DataPort |
| Date of data production | 20 Nov 2022 |